Chip Design Expert (RTL Design & Verification)

Overview

Mercor is hiring experienced RTL design and verification engineers to review chip design tasks used to train and evaluate AI models. The work involves assessing realistic hardware engineering problems such as designing or fixing an RTL block or writing a testbench. Each task includes a specification, starter files, a reference solution, and automated tests.

What You'll Do

• Review each task end to end, including the spec, starting files, reference solution, and tests.
• Check whether the task is fair and solvable, including whether the reference solution passes and the tests can be derived from the spec.
• Identify issues such as ambiguous specs, weak tests, leaked answers, or tasks that are easier than they appear.
• Judge whether the task is difficult enough to challenge current AI models.
• Write clear feedback, suggest fixes, and contribute ideas for new tasks.

Who We're Looking For

• 5+ years of hands-on RTL design or verification experience in industry such as semiconductor, FPGA, or EDA.
• Strong Verilog/SystemVerilog skills, plus experience with simulation and testbenches.
• Ability to read and reason about Python test code.
• Careful, skeptical reviewers who can explain in writing why a task is broken or too easy.
• Nice to have: experience with open-source EDA tools such as Icarus Verilog, Verilator, Yosys, or cocotb, as well as formal verification or reviewing AI benchmarks.

Schedule & Terms

• Remote and flexible, with about 15–20 hours per week.
• Independent contractor engagement.
• Work may be extended, shortened, or concluded early depending on project needs and performance.
• Work is fully remote and can be done on your own schedule.
• Payments are made weekly on Stripe or Wise based on services rendered.
• This role does not involve access to confidential or proprietary information from any employer, client, or institution.
• Mercor is unable to support H1-B or STEM OPT candidates at this time.